Analog Devices AD805 155 Mbps data retiming phase-locked loop (PLL) IC introduces a new clock recovery method that eliminates Type A/B interworking incompatibility. This VCXO circuit can be used to create a highly accurate 155-MHz clock from a system c lock running typically at 19.44 MHz or 25.92 MHz.
Technology:
unknown
Package:
DIP 20 Pin
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