AMCC (Applied Micro Circuits Corporation ) : S3029

SONET/SDH 155 Mbit/s Quad transceiver

The function of the S3029 clock synthesis and recovery unit is to derive high speed timing signals for SONET/SDH-based equipment. The S3029 is implemented using AMCC\'s proven Phase Locked Loop (PLL) technology. The S3029 receives four STS-3/STM-1 scrambled NRZ signals and recovers the clock from the data and generates a 155 MHz transmit clock. The chip outputs a differential PECL bit clock and retimed data. The S3029 utilizes five on-chip PLLs which consist of a phase detector, a loop filter, and a voltage controlled oscillator (VCO). The phase detector compares the phase relationship between the VCO output and the serial data input. A loop filter converts the phase detector output into a smooth DC voltage, and the DC voltage is input to the VCO whose frequency is varied by this voltage. A block diagram is shown in Figure 2. There is a single clock multiplier PLL which generates a 155 MHz transmit clock from a 19.44 or 51.84 MHz input. Features are

• Complies with ANSI, Bellcore, and ITU-T specifications for jitter tolerance, jitter generation
• Five on-chip high frequency PLLs with internal loop filters for clock recovery
• Supports clock recovery for STS-3/STM-1 (155.52 Mbit/s) NRZ data
• Clock Multiplier PLL for transmit clock generation
• 19.44 or 51.84 MHz reference frequency
• Lock detect-monitors run length and frequency
• Low-jitter differential interface
• 3.3V supply
• Available in a 64-pin TQFP package
• Compatible with IgT WAC-413 ATM Quad-UNI processor

Information used to be available at:

http://www.amcc.com/Products/Sonet/prod_59.htm

Technology:	unknown
Package:	PQFP 64 Pin

http://www.amcc.com/pdfs/s3029.pdf