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TC35821F The 155Mbps framer contains clock recovery circuits, byte alignment and frame synchronization, frame descrambling, frame overhead analysis, ATM cell synchronization, ATM cell header error correction and ATM cell payload descramble functions. Its transmit functions include ATM cell payload scramble, ATM header error correction (HEC) generation, frame overhead generation, frame assembly and frame scrambling. In addition, access to the chip registers from the central processing unit is available for configuration, status, memory, test plus error counter and cell counter. This device supports SONET standards STS-3C, STS-1, STS-1 half, and SDH at STM-1. It contains a 155.52 megahertz (MHz) pseudo emitter coupled logic serial line interface to the transceiver chips and a cell interface based on UTOPIA Level 2. The device offers programmable section overhead (SOH)/path overhead (POH) handling and operates internally at 19.44MHz/6.48MHz with a maximum 40MHz cell-interface operation. Designed in 0.6 micron CMOS technology, it operates on a single +5.0 volt single power supply.
Technology: | unknown |
Package: | unknown 0 Pin |
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