AMCC (Applied Micro Circuits Corporation ) : S3020/S3021

ATM 622 Mbit/s Transmitter and Receiver

The S3020/S3021 ATM transmitter and receiver chips are fully integrated serialization/deserialization ATM 622 Mbit/s interface devices. The chipset performs all necessary serial-to-parallel and parallel-to-serial functions in conformance with ATM transmission standards. The devices are suitable for SONET-based ATM applications. The figure below shows a typical network application.

On-chip clock synthesis is performed by the high-frequency phase-locked loop on the S3020 transmitter chip allowing the use of a slower external transmit clock reference. Clock recovery is performed on the S3021 receiver chip by synchronizing its on-chip VCO directly to the incoming data stream. The S3021 also performs ATM frame detection. The chipset can be used with a 19.44 or 77.76 MHz reference clock, in support of existing system clocking schemes.

The low jitter PECL interface guarantees compliance with the bit-error rate requirements of the Bellcore, ANSI, and ITU-T standards. Features are

• Complies with ANSI, Bellcore, and ITU-T specifications
• On-chip high-frequency PLL for clock generation and clock recovery
• Supports 622.08 Mbit/s (OC-12/STM-4)
• Reference frequencies of 19.44 and 77.76 MHz
• Interface to both PECL and TTL logic
• 8-bit TTL datapath
• Diagnostic loopback mode
• Lock detect
• Low jitter PECL interface
• < 2.0 Watt per set typically

The part is packaged in 52 PQFP TEP.

Technology:	unknown
Package:	PQFP 52 Pin