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ATM Switching Preprocessor DownstreamFeatures include
- Interfaces directly to ATM switching networks built with ASM chips
- Throughput 150 Mbps
- OAM functions according to ITU-T I.610 and Bellcore 1248:
- - Alarms: generation of AIS/RDI cells for all connections (F4 and F5)
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- - Continuity check: automatic for all connections
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- - Loopback: automatic loop of LB cells
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- - Performance monitoring: complete HW support for up to 64 connections
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- Double switch plane support for redundant fail save switching systems
- System Control Information Flow via SLIF Datalink supported
- Use external SDRAMs for storage of connection related data
- 16-bit general purpose microprocessor interface
- JTAG boundary scan
- Two high speed serial inputs with individual bit phase
adaptation
- Adaption from switch internal SLIF cell format (64 octet) to
standard cell format
(53 octet):
- - removal of routing header
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- - evaluation of
synchronization octet, checksums and cell sequence number
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- - removal of SLIF empty cells for cell rate decoupling
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- Redundant path combining function selectable per
connection
- Spatial multicast with individual header translation
for each branch
- Logical multicast for an arbitrary number of branches
- Built-in 350 cell deep buffer for data rate adaption
- Support of 1, 3, 4 and 8 output queues in a shared buffer
- Cell counting functions according to Bellcore TA-NWT-1248
- Header translation to any combination of VPI/VCI
- Multiport UTOPIA interface for up to 4 PHYs
Technology: | unknown |
Package: | BGA 342 Pin |
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