PMC (PMC Sierra Inc. ) : PM 5348

S/UNI-Dual

• Provides two independent SATURN(R)-Compatible ATM PHY channels in one chip.
• Provides hardware and software backwards compatibility with the industry-standard PM5346 S/UNI-155-LITE chip.
• Implements the ATM transmission convergence (TC) sub layer according to ATM Forum specifications using the SONET/SDH 155.52 Mbit/s STS-3c/STM-1 and SONET 51.84 Mbit/s STS-1 formats.
• NRZ data format supports category-5 unshielded twisted pair (UTP-5) or shielded twisted pair (STP) wiring and optical data link modules for fiber optic cable.
• Includes on-chip clock recovery and clock synthesis, compliant to Bellcore and ITU-T requirements.
• Operates in timing master or timing slave (loop timed LAN) modes.
• Frames to SONET framing bytes (A1, A2), processes the section and line Bit Interleaved Parity (B1, B2) and the Far-End Block Error (Z2) bytes.
• Interprets the H1, H2 and H3 payload pointer bytes.
• Processes the SONET path overhead BIP-8 (B3), signal label (C2) and path status (G1) bytes.
• Allows for protection switching by monitoring the APS (K1, K2) bytes, bit error rate thresholds and far-end synchronization status (S1) bits and providing interrupts when error conditions are detected.*
• Inserts and extracts ATM payloads using ATM cell delineation.
• Provides on-chip four-cell FIFO buffers in both transmit and receive paths.
• Operates with a backwards compatible dual 8-bit plus parity or a multi-PHY compatible 16-bit plus parity* SATURN-Compliant Interface for Physical layer devices (SCI-PHY). Cell interface is also compatible with ATM Forum Level-2 Utopia direct-mode specifications.
• Provides a generic 8-bit microprocessor bus interface for configuration, control and monitoring.
• Provides TTL/CMOS compatible inputs and outputs and differential PECL inputs.
• Low power, +5 Volt CMOS technology.

Technology:	0.35µ CMOS
Package:	PQFP 160 Pin