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ATM Switching Preprocessor UpstreamFeatures include
- Interfaces directly to ATM switching networks built with ASM chips
- Throughput 150 Mbps
- OAM functions according to ITU-T I.610 and Bellcore 1248:
- - Alarms: generation of AIS/RDI cells for all connections (F4 and F5)
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- - Continuity check: automatic for all connections
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- - Loopback: automatic loop of LB cells
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- - Performance monitoring: complete HW support for up to 64 connections
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- Double switch plane support for redundant fail save switching systems
- System Control Information Flow via SLIF Datalink supported
- Use external SDRAMs for storage of connection related data
- 16-bit general purpose microprocessor interface
- JTAG boundary scan
- Multiport UTOPIA interface supports up to 4 PHYs
- Cell header verification
- Cell Header Reduction in 3 modes to up to 8k connections
- Policing according to ITU I.371 and ATM Forum for all connections
- OAM functions according to ITU-T I.610 and Bellcore 1248:
- - Alarms: generation of AIS/RDI cells for all connections (F4 and F5)
-
- - Continuity check: automatic for all connections
-
- - Loopback: automatic loop of LB cells
-
- - Performance monitoring: complete HW support for up to 64 connections
-
- Adaption from standard cell format (53 octet) to the switch internal
SLIF cell format
(64 octet):
- - addition of routing header
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- - generation of synchronization octet, checksums and cell sequence
number
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- - insertion of SLIF empty cells for cell rate decoupling
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- 2 SLIF outputs to support redundant switch planes
Technology: | unknown |
Package: | BGA 342 Pin |
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web page used to be available at: http://www.siemens.de/Semiconductor/products/ICs/33/ATM/index.htm
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