Agere (Agere Systems ) : ATLANTA

Switching fabric chipset

The ATLANTA switch chip set, developed by Bell Laboratories, addresses the challenge to produce a cost-effective, high-performance, nonblocking switch architecture that can scale over a wide range of switch fabric capacities (0.5 Gbits/s to 25 Gbits/s). The chip set architecture is also scalable in number of cell buffers for congestion (up to 64,000 cells per port); number of virtual connections ( up to 64,000 connections per port); and line interface speeds (T1 rates to OC-12 SONET rates). In addition, it provides an unprecedented level of integrated features for traffic, congestion, and switch management. The chip set incorporates powerful features such as multiple quality of service (QoS) classes, high-performance multicasting, ATM-Forum-specified "dual leaky bucket" traffic policing (for rate monitoring), available bit rate (ABR) flow control, and frame discard. In addition, a built-in fault tolerance feature allows for the addition of a second redundant switching fabric with automatic cutover under system control if the primary fabric fails. The ATLANTA chip set consists of four VLSI devices. The ATM Layer Manager (ALM) performs user-to-network interface (UNI) or network-to-network interface (NNI) management functions on as many as 30 full-duplex physical (PHY) ports with an aggregate bandwidth of up to 622 Mbits/s. The ATM Buffer Manager (ABM) incorporates highly flexible schemes for cell buffering, queue management, and scheduling. The ALM and ABM devices can be used together to create port cards for an ATM switch or to build a complete ATM multiplexor/concentrator with up to 30 full-duplex PHYs.

Technology:	unknown
Package:	unknown 0 Pin

http://www.agere.com/telecom/docs/PN96068.pdf