|
- Previous: µPD98411 (NEASCOT-P40)
- Up: List all categories
The WAC-187-A ATM Routing Table uses multi priority queuing algorithms to allow delay-sensitive data to be multiplexed with general LAN traffic. The ATM Routing Table provides per-VC, per-priority, and per-device congestion thresholds with hysteresis which selectively enable the AAL5 early packet discard, EFCI marking, and/or CLP cell dropping congestion management algorithms for up to 4096 channels. In addition, per-VC, per-priority, and per-device maximum queue depth thresholds are provided. It also provides an OAM interface, header translation, and statistics. The ATM Routing Table connects between a UTOPIA interface and a switch fabric composed of ATM Switch Elements ( WAC-188-A) or other devices. It also interfaces to a processor, external SRAM, and a JTAG controller. The external RAM is used for input buffering of 512, 3027 or 7168 cells. Output buffering is internal.
Technology: | unknown |
Package: | unknown 0 Pin |
|
web page used to be available at: http://www.igt.com/Documentation.htm
If you are the producer of this chip and want to correct/update the presented information, please feel free to register for direct database access.
|