Advance (Advance Logic Corporation ) : ALC-ATM-103

Segmentation & Reassembly Processor

The SAR block from Advancel Logic Corporation is a high performance ATM (Asynchronous Transfer Mode) controller described in Verilog HDL at RTL Level. The controller can be synthesized into logic gates of a target foundry using Synopsys synthesis tools and the target cell library. The SAR block implements ATM protocol layer and adaptation layer (AAL) functions. It interfaces directly to the host via a 32 bit PCI interface and uses an advanced architecture to minimize the CPU and PCI bus utilization. The segmentation and re-assembly of ATM cells are performed directly in the host memory eliminating the need for on-board memory for storing cell data which results in a significant cost savings for the ATM NIC. It uses data structures initialized by the host in the control memory to perform segmentation and reassembly functions with minimum intervention from the host. The architecture supports up to full 64K simultaneously open VCs at full duplex line rates of up to 622 Mbps. The SAR block performs all AAL-5 functions including segmentation and re-assembly (SAR). During receive, ATM cells received are re-assembled into PDUs in the host memory. During transmit, the PDUs are segmented and processed by the SAR block into ATM cells. The SAR block perfroms CRC-10 generation and checking for RM cells. The SAR block implements ABR flow control specified in the ATM Forum's 4.0. It automatically generates forward RM cells and retrieves backward RM cells and adjusts the outgoing rate for the ABR traffic as per the parameters in the backward RM cells. The destination behavior for ABR flow control is also implemented in the SAR block. The received forward RM cells are updated and turned around as reverse RM cells. The SAR block implements the utopia interface for connection to physical layer devices. The utopia interface conforms to the ATM Forum level 1 specifications.

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