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ATM Chip Database |
- Previous: µPD98411 (NEASCOT-P40)
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Infineon (Infineon Technologies AG ) : PXB 4110
SARE
Features include
- AAL 3/4 and 5 segmentation and reassembly
- Transparent mode to support constant bit rate traffic
- On-chip support for 60 virtual connections
- Optional ext. RAM supports up to 64K virtual connections
- 32 bit PCI system bus interface (33MHz)
- UTOPIA Level 1 interface
- Built-in 2+10 cell receive and 4 cell transmit FIFO
- Full duplex transfer rate 155.52 Mbit/s
- VC level OAM cell detection and CRC-10 calculation
- Cell rate shaping in transmit direction with up to 8 (dual) leaky buckets
- Bus master DMA with linked list structure and programmable buffer length
- Built-in MMU with packet scatter/gather capability
- Built-in data path loops for self-test purpose
- JTAG boundary scan according to IEEE 1149.1
Technology: 0.35µ CMOS Package: PQFP 208 Pin
web page used to be available at: http://www.siemens.de/Semiconductor/products/ICs/33/ATM/index.htm
If you are the producer of this chip and want to correct/update the presented information, please feel free to register for direct database access.
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Last update:
14.11. 2009
Last link check: 01.03. 2006 |
All registered names and trademarks are the property of their respective owners. No guarantee is given and no responsibility is taken for the information provided. © 2024 Thomas Martin Knoll knoll@chipweb.de Impressum Datenschutz |
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