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ATM Chip Database |
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Conexant (Conexant Systems, Inc. ) : Bt8233EVS
ATM xBR Service Segmentation & Reasembly Controller
The Bt8233 consists of five separate coprocessors (Incoming & Outgoing DMA, Segmentation, Reassembly and xBR Traffic Manager), each of which maintains state information in shared, off-chip memory. This memory is controlled by the SRC through the local bus interface, which arbitrates access to the bus between the various coprocessors. These coprocessors, though they run off the same system clock, operate asynchronously from each other. Communication between the coprocessors takes place through on-chip FIFOs or through queues in local memory. Designed as a total solution for UNI 3.1 and TM4.0, the Bt8233 provides automated segmentation and reassembly processes in silicon. The Bt8233 service-specific features allow system designers to accelerate specific protocol interworking functions for applications like Frame Relay or LAN Emulation. In addition, the device's unique architecture enables advanced network-level functionality and topologies.
Integrated Management
The Bt8233 complies with ATM Forum specifications UNI 3.1, TM4.0, and all other relevant standards. The Bt8233 provides integrated traffic management for all service categories, including Constant Bit Rate (CBR), Variable Bit Rate (VBR) (single and dual leaky bucket), real-time VBR, Unspecified Bit Rate (UBR), Available Bit Rate (ABR) and Generic Flow Control (GFC); thus, the term, xBR SAR. The xBR Traffic Management block automatically schedules each VCC according to user assigned parameters to maximize line utilization.Advanced Architecture
The Bt8233's architecture is designed to minimize and control host traffic congestion. The host manages the Bt8233 terminal using write-only control and status queues. The control queues are also isolated from their associated data buffers via buffer descriptors, allowing the data buffers to hold payload data only. For example, the host submits data for transmit by writing buffer descriptor pointers to one of 32 Transmit Queues. These entries may be thought of as task lists for the ServiceSAR to perform. In addition, the Bt8233 can perform ATM server functions for up to 32 clients. The Bt8233 enables control of traffic congestion through mechanisms like Receive Buffer memory limitations (called firewalls) and through explicit notification of congestion by the host. This architecture lessens the control burden on the host system while minimizing PCI bus utilization by eliminating reads across the PCI bus from host control activities. It also provides control points to manage congestion, which is critical for ABR.- 4 PCI slots per host PCI bridge (8 total slots)
- Hardware interface fully compliant to PCI
- 2 MB Flash, 32 MB DRAM on Host (expandable to 128 MB DRAM, 4 MB Flash)
- Hardware reference design
- Software reference design
- Traffic Generation and checking capability
- Optical STS-3c interface
- Third party products/support available
Technology: unknown Package: unknown 0 Pin
web page used to be available at: http://www.nb.rockwell.com
If you are the producer of this chip and want to correct/update the presented information, please feel free to register for direct database access.
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Last update:
14.11. 2009
Last link check: 01.03. 2006 |
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